When: January 2021 (it is the entire month)

What: WINTERHEAT 2021 is a month long amateur radio simplex event.

Why: The goal and purpose is for amateur radio operators to make as many contacts as possible over a month long period of time using only designated simplex frequencies.

CLICK for DETAILS

CLICK for GUIDELINES

You may use the Payment Gateway to pay 2021 dues.
 
CLICK HERE for 2021 Dues Payment Gateway

Our membership period is January 1 to December 31.

Renewals began on October 1st. The grace period ends on March 31

We look forward to a full year of many projects even with COVID-19 and yes the Member tools are always undergoing updates. Please be watching for a list of what BRARA has accomplished and what we're planning in 2021.
 
Thank you for your support which is vital to our success.

On 1-Jan-2021 all 2021 Paid Members had their Administrative Year updated from 2020 to 2021.

How can you tell if you have not paid your 2021 dues? There are two ways.

1. No logon permitted if Admin Year was 2019 or earlier.

2. On home page see message "2021 dues payable by 2021-03-31."

In either case, to resolve this, please visit our Payment Gateway to Pay 2021 Dues.

Please Note
Any member who has yet to renew for 2021 continues full privileges and benefits of Membership until 31-March-2021.
 
NOTE: If you have paid your dues and have NOT received an email confirming payment, please contact Michael Greenfeld by email k8bq@arrl.net

The following are some Membership statistics as of 7-JAN-2021. Please note these numbers are vastly different from prior BRARA Weekly Updates because we rolled into a NEW YEAR. 

E9E09 (C)
Which of the following is used to shunt-feed a grounded tower at its base?
A. Double-bazooka match
B. Hairpin match
C. Gamma match
D. All these choices are correct

E7A08
What logical operation does an OR gate perform?
A. It produces logic 1 at its output if any or all inputs are logic 1
B. It produces logic 0 at its output if all inputs are logic 1
C. It only produces logic 0 at its output when all inputs are logic 1
D. It produces logic 1 at its output if all inputs are logic 0